About Company

Company has a vision to provide smart and affordable solutions to all companies/ individuals who are engaged in technological development of the human race. This way, we can contribute to make life of human kind better globally.

In order to serve this objective we have introduced our first Electronic Design Automation (EDA) tool product atssim. This is a systemverilog HVL(Hardware Verification Language) / HDL (Hardware Design Language) simulator, which supports UVM (Universal Verification Methodology). UVM is most advanced and popular verification methodology used for functional verification of hardware designs (known as System on Chip (SoC) ).