We are excited to introduce the ATSSIM simulator to the global ASIC/SoC design and verification community. At Avinya Technology Systems, we are dedicated to empowering designers to tackle complex SoC designs with ease. Our simulator is designed to support all advanced features of SystemVerilog, including assertions, Functional Coverage, Direct Programming Interface (DPI), and Universal Verification Methodology (UVM) compatibility.
This endeavor presents a remarkable opportunity for our team to engage with our clients in an interactive manner, understanding their specific needs, and implementing relevant improvements to enhance the product's performance. We sincerely request all users to share their issues and requirements with us. Your valuable feedback will enable us to provide you with the best possible solutions.
We extend our heartfelt gratitude to all users for entrusting us with the privilege to serve you. Rest assured, we remain committed to offering unwavering support for the ATSSIM simulator.
With Warm Regards,
Team Avinya Technology Systems