Design simulator tool is developed to compile and simulate verilog/ systemverilog designs and verification environment as per IEEE Standard for SystemVerilog – Unified Hardware Design, Specification, and Verification Language (IEEE std 1800-2012).
Following are indicative features of Systemverilog, which are supported by simulator.
Please, refer chapter 1 to 7 and 9 to 13 of IEEE std 1800-2012. All features in these chapters are implemented except few relatively less used features which are listed in scheduled to be added features below.
Static class properties, Static methods, Inheritance, Virtual Methods, Polymorphism, Out-of-block declaration, Parameterized classes etc. Please, refer chapter 8 of IEEE std 1800-2012.
refer chapter 14 of IEEE std 1800-2012
Interprocess synchronization and communication
mailboxes and semaphores
Constrained random value generation
random methods (randomize(), rand_mode(), constraint_mode() etc.). refer chapter 18 of IEEE std 1800-2012.
Covergroup, Coverpoint, Cross, bins and crossbins support. Option and type_option structure member support.
Utility and I/O system tasks
Most of utility and Input/ Output system tasks and functions are supported. Please, refer chapter 20 and 21 of IEEE std 1800-2012.
All commonly used compiler directives are supported. Please, refer chapter 22 of IEEE std 1800-2012.
Module,Program, Interface, Package and generate block support
Please, refer chapter 23,24, 25, 26 and 27 of IEEE std 1800-2012.
Immediate and Concurrent Assertions.
Gate level and Switch level Models
Gate (and, buf etc.) and switch (tran, tranif0 etc.) level model implementation.
Direct Programming Interface (DPI)
DPI suppport for C/ C++ import / export function or task is available. C/C++ models of verification components can be seamlessly integrated in verification environment. Please, refer chapter 35 of IEEE std 1800-2012.