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UVM Features

Next-Gen Solutions

What is UVM

Universal Verification Methodology (UVM) is an automated and customizable verification framework written in Systemverilog. This HDL design verification framework empowers verification engineer to create a very efficient verification environment (testbench) to test a complex designs within a short time. UVM leverages re-usability of the verification components to reduce time and labor required to create verification environment.


How to know more about UVM

UVM framework is developed by one of the working groups of accellera ( please, visit accellera.org for more information and downloading of UVM package for free).

Tested features of UVM package

atssim simulator has been successfully tested to run all example testcase supplied with uvm-1.2 package.