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FAQs Technical Support

Next-Gen Solutions

Q. 1. How to run compiler and simulator?

Please follow few steps as under to compile and simulate your design:

  • If you have defined ATSSIM_LIC_PATH and ATSSIM_PKG_PATH environment variables as described in support main menu, create a work directory in any name and go to that directory.
  • If ATSSIM_LIC_PATH and ATSSIM_PKG_PATH environment variables are not defined then user must work in directory, where atssim license and atssim package is stored.
  • User can run atssim in following 2 modes.

Command Mode:  User can compile or simulate any source file with a single command as under:

cmd_prompt>exeatssim -top [top_module_name] [source_code_files] 

Interactive Mode: run atssim command on command prompt and you enter in interactive mode.

cmd_prompt>exeatssim

Note:

  1. Use exeatstsim instead of exeatssim for trial version of simulator.
  2. Designs with DPI export/ import functions can be compiled and simulated in command mode only, right now.

Q. 2. How to get help on command line simulation options?

In command mode give a command as under and you will get all available options.

cmd_prompt>exeatssim -help

In interactive mode you can type help and you will get all compilation and simulation options on screen.

Note:

  1. Use exeatstsim instead of exeatssim for trial version of simulator.

Q. 3. What will be my simplified simulation flow?

When you will invoke atssim to simulate any source code, atssim will run following 3 phase in that order:

  1. Compilation phase: Atssim will compile your source code first and show all syntactical errors. You need to make all necessary changes in your source code (as per systemverilog LRM), which are shown as errors in compilation phase. Atssim will not move to next phase unless all compilation errors are resolved.
  2. Elaboration phase: Once there is no compilation error in source code, design will undergo elaboration phase. This phase creates storage for variables/ objects and entities and provides necessary interconnection between created objects and entities. This phase also initializes all variable and entities with their default values as defined in source code.
  3. Simulation phase: Successfully elaborated design moves in simulation phase and simulates design in a virtual time domain. There may be run time errors in design, which may not figure out at compile or elaboration time. Designers must watch simulation log carefully to remove run time errors in design.

Q. 4. Where is compiled package database library?

Whenever any package is compiled successfully then atssim creates a folder named ‘atspackage’ in same working directory. All compiled packages database are saved in this folder with a name convention <package_name>.db. Once a package database is compiled and saved in atspackege folder, this can be used by designer in any design using export <package_name>.* systemverilog construct.

Q. 5. If my design has multiple packages with same name then which one will be used?

Whenever a design is compiled or simulated, all defined packages in that design are saved in atspackage folder. Therefore, atssim will pickup most recently compiled package if you have multiple packages with same name.

Q. 6. How can I update my package to most recent version of atssim package?

As long as your license is valid user can give ‘sudo atssim -update‘ command to update atssim package. Please ensure that you are connected to internet and logged in as root user.

Q. 7. How to run uvm testcase?

We suggest following procedure to run uvm testcase:

  • current version supports uvm 1.2, therefore download uvm 1.2 package and extract it in a folder.
  • First of all compile uvm.sv file to get uvm_pkg databse in atspackage folder of your working folder. The compilation will take 3 – 8 minutes based on the speed of your machine/ server. We recommend to create uvm_pkg.db file in atspackage folder so that for any subsequent uvm based testcase, you need not to recompile whole uvm_pkg, but you shall directly export it in your design. Thus making simulation process faster.
  • The above compilation activity is a one time and then you can use compiled uvm_pkg in all your subsequent testbench without bothering to compile it again.
  • Now to create any uvm based verification environment add export uvm_pkg.* in the beginning of your testbench to export whole uvm_pkg from atspackage folder within fraction of second. We also suggest to replace all code lines with `include uvm.sv by export uvm_pkg.* in your source code to avoid recompilation of uvm_pkg.

NOTE:

Above FAQ is under constant upgrade based on questions asked by users and updates made by us in simulator package.