Hi All,
I extend my warm greetings to all users of atssim simulator.
Its my pleasure to present beta version of atssim compiler and simulator to front end ASIC/SoC design and verification community worldwide. This compiler and simulator supports assertions, Functional Coverage, Direct Programming Interface (DPI) and Universal Verification Methodology (UVM) in order to empower designers to handle complex SoCs.
Beta release of tool is currently available for beta testing partners.
In my view, it will be a great opportunity for me and my team to serve our clients in an interactive and realistic way after understanding their needs and then making all required changes in this product for better performance. I have a humble request to all users to share their issues and requirements with us and consequently, we shall look forward to provide them best possible solutions.
We have a roadmap to add new features in this product and enrich existing features, however, it will be a great and encouraging experience if we receive valuable and relevant suggestions from users.
I convey my best wishes to all users for successful completion of their design and verification efforts and reiterate our commitment to provide best possible support on atssim simulator.
Note: Companies or individuals, who are interested to participate in beta testing of tool must contact at partner@avinyatechnology.com